Frequency Multipliers

Posted on Feb 5, 2014

J1 And J2 are a matched pair of J310`s (can also use U310`s or a U431 matched pair). R2 is selected to bias the 2 FETs with a small drain current with no RF input. The turns ratio of the input transformer is selected for an approximate 50 ohm impedance match at the transformer primary (L1). The combined drain current waveform is a rectified sinewave superimposed on a small dc offset (see below).

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At UHF it is desirable to reduce the drain load impedance and the impedance seen by the JFET sources, thus higher Idss low capacitance JFETs are required. Higher frequency operation is possible if Guanella baluns are substituted for the input and output transformers. N. B. for clarity no parasitic suppression components are shown in the schematic. As shown in the (LTSpice) simulated waveforms shown above the drain current waveform is a rectified sinewave with a small dc current superimposed. There is also a small predominantly 2nd harmonic component of drain current flows via the drain gate capacitance of the JFET. This is particularly evident when the source current of each JFET is cutoff. NB the JFETS perform the frequency doubling principally by switching action and not due to the JFET square law input characteristic. The output frequency spectrum of the doubler for a 10MHz +13dBm input as seen at the load is displayed below (reference level is 1V rms). The output level of the frequency doubled component (20MHz)is slightly more than +13dBm. The low phase noise common base BJT frequency doubler shown above is capable of very good performance despite the fact that it uses inexpensive transistors. The low dc gain from base to collector of the dual transistor coupled with the emitter degeneration ensures low phase noise. The circuit is intended for use with 5MHz or 10MHz input frequencies. Like all frequency doublers it has...

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