Frequency Locked Loop for HF
Description: The principle of operation is quite simple, a counter measures the VFO frequency, the new reading is compared with the previously stored value and an adequate correction is applied consequently. This process has been implemented in the past using several discrete TTL logics, now a single microprocessor can do the job much better, moreover offering a digital readout capability. The best way seemed to be a D/A converter, driven by the PIC so as to produce a control voltage towards a varicap diode, but it would have required at least a 10 bit (better 12 bit) resolution, a component not so cheap nor so easy to find. So I considered to employ a different microprocessor, the PIC16F628. This device offers a built-in PWM module capable of delivering a 4 KHz square wave whose duty cycle may be software controlled with an accuracy of 10 bit. It was enough to add a simple RC integrator to obtain a well filtered control voltage, variable from 0 to 5V with a 1024 steps resolution. Such a circuit may control the VFO frequency in a 15 KHz range with a 15 Hz unit step, notice that a single frequency adjustment is applied only when a certain drift amount is measured and, unlike a PLL system, there is no stability problem, no elongation or settling time, so it is possible to obtain a quite clear VFO signal, with a very low noise level. Just what I was looking for. In short, the main performance of this device are: · Frequency stability aligned to the reference crystal, with a maximum +/- 15 Hz drift · Digital frequency readout, with programmable IF value and 10 Hz resolution on the LCD display · Manual frequency tuning, through a multi-turn potentiometer · Automatic Lock/Unlock function, unlock status is signalled by a LED diode and entered during manual tuning or in case of an excessive VFO drift · Programmable lock range. It is the maximum allowed value for a short term” (0.2 sec) frequency shift without exiting the locked status. This improves the capability to suit to various VFO circuits. · The overall (long term) drift compensation capability is limited to about 15 KHz (+/- 7.5 KHz), normally enough to stabilize a well assembled VFO, however I suggest not to exceed a 20/25 MHz limit, although the counter capability may reach 35/40 MHz.
The described circuit operates by utilizing a counter to measure the frequency of a Voltage-Controlled Oscillator (VFO). The new frequency measurement is compared against a previously stored value, and a correction voltage is generated based on this comparison. The implementation of this function has evolved from using discrete TTL logic components to a more efficient microprocessor-based solution, specifically the PIC16F628. This microcontroller features a built-in Pulse Width Modulation (PWM) module that can generate a square wave at 4 kHz. The duty cycle of this PWM signal can be adjusted in software, providing a resolution of 10 bits, which is sufficient for the application.
To convert the PWM signal into a smooth control voltage, an RC integrator circuit is employed. This circuit filters the PWM output to produce a variable control voltage ranging from 0 to 5V, with a resolution of 1024 steps. This control voltage is then used to adjust the frequency of the VFO, allowing for precise tuning within a range of 15 kHz, with a minimum step size of 15 Hz.
The circuit includes several key features that enhance its performance and usability. Frequency stability is maintained in alignment with a reference crystal, with a maximum drift of ±15 Hz. A digital readout capability is provided, displaying the frequency on an LCD with a programmable Intermediate Frequency (IF) value and a resolution of 10 Hz. Manual tuning is facilitated through a multi-turn potentiometer, allowing for fine adjustments.
An Automatic Lock/Unlock function is integrated into the design, indicated by an LED. This feature enables the system to unlock the frequency adjustment during manual tuning or if excessive drift is detected. Additionally, the programmable lock range allows for a defined maximum short-term frequency shift (0.2 seconds) without exiting the locked state, enhancing adaptability to various VFO circuits.
The overall drift compensation capability is limited to approximately 15 kHz (±7.5 kHz), which is generally sufficient for stabilizing a well-constructed VFO. However, it is advisable to keep the frequency range within 20 to 25 MHz, despite the counter's capability to handle frequencies up to 35 to 40 MHz. This design ensures a clear VFO signal with minimal noise, meeting the requirements for a reliable frequency control system.The principle of operation is quite simple, a counter measures the VFO frequency, the new reading is compared with the previously stored value and an adequate correction is applied consequently. This process has been implemented in the past using several discrete TTL logics, now a single microprocessor can do the job much better, moreover offering a digital readout capability.
The best way seemed to be a D/A converter, driven by the PIC so as to produce a control voltage towards a varicap diode, but it would have required at least a 10 bit (better 12 bit) resolution, a component not so cheap nor so easy to find. So I considered to employ a different microprocessor, the PIC16F628. This device offers a built-in PWM module capable of delivering a 4 KHz square wave whose duty cycle may be software controlled with an accuracy of 10 bit. It was enough to add a simple RC integrator to obtain a well filtered control voltage, variable from 0 to 5V with a 1024 steps resolution.
Such a circuit may control the VFO frequency in a 15 KHz range with a 15 Hz unit step, notice that a single frequency adjustment is applied only when a certain drift amount is measured and, unlike a PLL system, there is no stability problem, no elongation or settling time, so it is possible to obtain a quite clear” VFO signal, with a very low noise level. Just what I was looking for. In short, the main performance of this device are : · Frequency stability aligned to the reference crystal, with a maximum +/- 15 Hz drift · Digital frequency readout, with programmable IF value and 10 Hz resolution on the LCD display · Manual frequency tuning, trough a multi-turn potentiometer · Automatic Lock/Unlock function, unlock status is signalled by a LED diode and entered during manual tuning or in case of an excessive VFO drift · Programmable lock range.
It is the maximum allowed value for a short term” (0.2 sec) frequency shift without exiting the locked status. This improves the capability to suit to various VFO circuits. · The overall (long term) drift compensation capability is limited to about 15 KHz (+/- 7.5 KHz), normally enough to stabilize a well assembled VFO, however I suggest not to exceed a 20/25 MHz limit, although the counter capability may reach 35/40 MHz.
The described circuit operates by utilizing a counter to measure the frequency of a Voltage-Controlled Oscillator (VFO). The new frequency measurement is compared against a previously stored value, and a correction voltage is generated based on this comparison. The implementation of this function has evolved from using discrete TTL logic components to a more efficient microprocessor-based solution, specifically the PIC16F628. This microcontroller features a built-in Pulse Width Modulation (PWM) module that can generate a square wave at 4 kHz. The duty cycle of this PWM signal can be adjusted in software, providing a resolution of 10 bits, which is sufficient for the application.
To convert the PWM signal into a smooth control voltage, an RC integrator circuit is employed. This circuit filters the PWM output to produce a variable control voltage ranging from 0 to 5V, with a resolution of 1024 steps. This control voltage is then used to adjust the frequency of the VFO, allowing for precise tuning within a range of 15 kHz, with a minimum step size of 15 Hz.
The circuit includes several key features that enhance its performance and usability. Frequency stability is maintained in alignment with a reference crystal, with a maximum drift of ±15 Hz. A digital readout capability is provided, displaying the frequency on an LCD with a programmable Intermediate Frequency (IF) value and a resolution of 10 Hz. Manual tuning is facilitated through a multi-turn potentiometer, allowing for fine adjustments.
An Automatic Lock/Unlock function is integrated into the design, indicated by an LED. This feature enables the system to unlock the frequency adjustment during manual tuning or if excessive drift is detected. Additionally, the programmable lock range allows for a defined maximum short-term frequency shift (0.2 seconds) without exiting the locked state, enhancing adaptability to various VFO circuits.
The overall drift compensation capability is limited to approximately 15 kHz (±7.5 kHz), which is generally sufficient for stabilizing a well-constructed VFO. However, it is advisable to keep the frequency range within 20 to 25 MHz, despite the counter's capability to handle frequencies up to 35 to 40 MHz. This design ensures a clear VFO signal with minimal noise, meeting the requirements for a reliable frequency control system.The principle of operation is quite simple, a counter measures the VFO frequency, the new reading is compared with the previously stored value and an adequate correction is applied consequently. This process has been implemented in the past using several discrete TTL logics, now a single microprocessor can do the job much better, moreover offering a digital readout capability.
The best way seemed to be a D/A converter, driven by the PIC so as to produce a control voltage towards a varicap diode, but it would have required at least a 10 bit (better 12 bit) resolution, a component not so cheap nor so easy to find. So I considered to employ a different microprocessor, the PIC16F628. This device offers a built-in PWM module capable of delivering a 4 KHz square wave whose duty cycle may be software controlled with an accuracy of 10 bit. It was enough to add a simple RC integrator to obtain a well filtered control voltage, variable from 0 to 5V with a 1024 steps resolution.
Such a circuit may control the VFO frequency in a 15 KHz range with a 15 Hz unit step, notice that a single frequency adjustment is applied only when a certain drift amount is measured and, unlike a PLL system, there is no stability problem, no elongation or settling time, so it is possible to obtain a quite clear” VFO signal, with a very low noise level. Just what I was looking for. In short, the main performance of this device are : · Frequency stability aligned to the reference crystal, with a maximum +/- 15 Hz drift · Digital frequency readout, with programmable IF value and 10 Hz resolution on the LCD display · Manual frequency tuning, trough a multi-turn potentiometer · Automatic Lock/Unlock function, unlock status is signalled by a LED diode and entered during manual tuning or in case of an excessive VFO drift · Programmable lock range.
It is the maximum allowed value for a short term” (0.2 sec) frequency shift without exiting the locked status. This improves the capability to suit to various VFO circuits. · The overall (long term) drift compensation capability is limited to about 15 KHz (+/- 7.5 KHz), normally enough to stabilize a well assembled VFO, however I suggest not to exceed a 20/25 MHz limit, although the counter capability may reach 35/40 MHz.
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