D0 Note xxxx
#VLPC
#front-end circuit
#charge signals
#SIFT chip
#fiber tracker
#preshower detectors
#L1 trigger system
#photon counters
Description: A front-end circuit has been developed for the D0 upgrade to read visible light photon counters (VLPCs) associated with the fiber tracker and preshower detectors. This custom chip, named SIFT, collects low-level charge signals from the VLPCs, provides discriminated signals to the L1 trigger system, and injects regenerated charge signals into an SVX-II based readout system. The chip's research and development phase is now complete. This note presents all relevant measurements concerning the operation of the SIFT. Initially designed as a trigger "pick-off" chip for the fiber tracker, the design parameters reflect the requirements for responding to minimum ionizing particles (MIPs) traversing scintillating fibers. However, the preshower detectors exhibit significantly different signal properties. A charge division technique has been developed to enhance the effective dynamic range and resolution of the SIFT, adapting it for reading out the preshower detectors. These studies will be reported in another note. The SIFT chip comprises 20 identical channels, with 18 active channels and 2 designated as guard channels. A functional overview of one channel of the SIFT chip is depicted in Figure 1. The front-end features an inverting charge-sensitive preamplifier with a switched capacitor (Cfb = 185 fF) in the feedback loop. The output from the preamp is directed to a buffer source follower that drives the AC-coupled discriminator and charge driver circuits. The charge driver circuit is complex as it must regenerate a charge impulse and feed it to the SVX in a DC-coupled mode. Consequently, the DC bias level at the input of the SVX chip must be offset by the SIFT. This task is complicated by a 20-30 mV variation in bias levels from channel to channel. To minimize spurious charge injection due to this variation, the output capacitance of the SIFT is kept small (100 fF) and well controlled. The preamp and buffer amplifier circuits are illustrated in Figure 2. To reduce noise at the front-end, a wide input transistor with high transconductance is employed. The speed of the integrating circuit is enhanced using a tree of biasing transistors, which reduces stray capacitance. However, during the reset phase, the standing current in the preamp is disturbed, leading to a prolonged recovery time to restore this current to its operational value. To expedite this recovery following the feedback capacitor reset, an internal pulse, PHDR, is generated across the capacitor C2 (125 fF). The charge induced by this pulse at the preamp output node restores the voltage to its operational point. An external voltage (VDR) controls the amplitude of this pulse. This method minimizes the duration of the reset pulse (PRST); successful operation of the chip has been achieved with a reset pulse width of only 5 ns, although a 10 ns pulse is recommended for normal operation. Figure 1 illustrates a simplified schematic diagram of one channel of the SIFT chip, highlighting the blocks comprising the preamplifier, discriminator, and charge transfer circuit, along with the three controlling voltages: V_DR, VCLMP, and VREF. The discriminator circuit, shown in Figure 3, functions by setting the input node bias at a voltage determined by another internally generated pulse, THSET, which is divided between capacitors C9 and C8. An external voltage (VTH) controls the height of this pulse. The effective threshold voltage of the discriminator is determined by the difference between the turn-on voltage of the input transistor and the voltage set at the input node. When the preamp output exceeds this difference, the discriminator input node activates, indicating the presence of a "hit." This transition is driven off-chip via a series of inverters when the S/H pulse is applied. Figure 4 depicts the charge driver circuit, which consists of two well-matched source followers with capacitors C6 and C7 across their outputs. Capacitor C7 can be removed from the circuit by turning off the GAIN_SEL switch; the following discussion assumes this is the case. The overall operation of the SIFT chip involves a RESET cycle (approximately 1 µs) followed by up to 56 ACQUISITION cycles (132 ns each), depending on the number of bunches in the Tevatron ring. The RESET cycle begins about 300 ns after the SVX reset, initiating with the PRST, DRST, READ, and PCLP switches closed. After 10 ns, PRST is released, allowing the preamp output to transition based on VDR. The output node is allowed to settle, and after approximately another 50 ns, the DRST switch is released. This action causes the THSET pulse to induce a small transition at the preamp output, determined by VTH. These transitions do not affect the outputs of the source followers (SF1 and SF2) in the charge driver circuit, as they are held at known values controlled by an external voltage (VCLP). The only variation in the output results from differences in the gains of the source followers. Meanwhile, capacitor C6 and other stray capacitors (to ground) are charged by the SVX reset current, with the voltage on C6 equal to the difference between the SVX input bias and VREF. After opening the READ switch and closing the S/H switch, capacitor C6 registers the voltage difference between SF1 and SF2. The PCLP switch is then opened, preparing the circuit for acquisition. During the ACQUISITION mode, the preamp is reset after each bunch crossing. To minimize charge injection at the source followers, PCLP is also exercised during the preamp reset.A front-end circuit has been developed for the D0 upgrade for reading out visible light photon counters (VLPC`s) associated with the fiber tracker and the preshower detectors. This custom chip, called SIFT, will be used to collect low-level charge signals from the VLPC`s, provide discriminated signals to the L1 trigger system and inject regenerate
d charge signals into an SVX-II based readout system. The chip R&D is now complete. In this note we present all the measurements that are relevant to the operations of the SIFT. The SIFT chip was initially designed as a trigger "pick-off" chip for the fiber tracker. Hence, the design parameters reflect the requirements of response to minimum ionizing particles (MIP`s) traversing scintillating fibers. The preshower detectors, however, have vastly different signal properties. We have developed a charge division technique in order to increase the effective dynamic range and resolution of the SIFT and adapt it for reading out the preshower detectors.
These studies will be reported in another note. The SIFT chip consists of 20 identical channels, of which 18 will be active and 2 are intended to be guard channels. Figure 1 shows a functional overview of one channel of the SIFT chip. The front-end is an inverting charged sensitive preamplifier with a switched capacitor Cfb (185 fF) in the feedback loop.
The output of the preamp is fed into a buffer source follower that drives ac-coupled discriminator and charge driver circuits. The function of the charge driver circuit is somewhat complicated because it has to regenerate a charge impulse and feed it to the SVX in a dc-coupled mode.
Hence, the dc bias level of the input of the SVX chip has to be offset by the SIFT. The problem becomes more challenging because there is a 20-30 mV variation from channel to channel in this bias level. In order to minimize spurious charge injection due to this variation, the output capacitance of the SIFT has to be small (100 fF) and well controlled.
The circuits used in the preamp and the buffer amplifier are shown in Figure 2. In order to reduce noise in the front-end, a very wide input transistor (with high transconductance) is used. The speed of the integrating circuit is enhanced by the use of a tree of biasing transistors, which step down the stray capacitance.
However, during reset the standing current in the preamp is disturbed and by itself the circuit takes a long time to restore this current to its operating value. In order to speed up this recovery after the feedback capacitor has been reset, an internal pulse, PHDR, is generated across the capacitor C2 (125 fF) capacitor.
The charge induced by this pulse at the preamp output node restores the voltage to its operating point. . An external voltage (VDR) controls the height of this pulse. This procedure allows us to minimize the duration of the reset pulse PRST; we have successfully operated the chip with a reset pulse width of only 5 ns but recommend a 10 ns pulse for normal operation.
Figure 1. : A simplified schematic diagram of one channel of the SIFT chip. The blocks consisting of the preamplifier, the discriminator and the charge transfer circuit are shown. The three controlling voltages, V_DR, VCLMP and VREF are highlighted. discriminator circuit is shown in Figure 3. It operates by setting the bias of the input node at a voltage determined by another internally generated pulse, THSET, which gets divided between the capacitors C9 and C8.
An external voltage (VTH) controls the height of this pulse. The difference between the turn-on voltage of the input transistor and the voltage set at the input node determines the effective threshold voltage of the discriminator. When the output of the preamp is large enough to overcome this difference the discriminator input node switches "on" signaling the presence of a ``hit".
When the S/H pulse is applied, this transition is driven off-chip via a series of inverters. Figure 2: The transistor level circuit diagram of the preamplifier. The voltage V_DR is asserted via an internally generated pulse (not shown) following preamp reset. The discriminator circuit is shown in Figure 3. It operates by setting the bias of the input node at a voltage determined by another internally generated pulse, THSET, which gets divided between the capacitors C9 and C8. An external voltage (VTH) controls the height of this pulse. The difference between the turn-on voltage of the input transistor and the voltage set at the input node determines the effective threshold voltage of the discriminator.
When the output of the preamp is large enough to overcome this difference the discriminator input node switches "on" signaling the presence of a ``hit". When the S/H pulse is applied, this transition is driven off-chip via a series of inverters. Figure 4 shows the charge driver circuit. It consists of two well-matched source followers that have two capacitors, C6 and C7, across their outputs.
The capacitor C7 can be removed from the circuit by turning off the GAIN_SEL switch; in the following discussion we will assume that this is the case. In order to understand the functionality of this circuit, we need to examine the overall operation of the SIFT chip, which consists of a RESET cycle (about 1 us) followed by up to 56 ACQUISITION cycles (132 ns each), depending on the number of bunches in the Tevatron ring.
The RESET cycle is initiated about 300 ns after the SVX reset and it starts with the PRST, DRST, READ and PCLP switches closed. After 10 ns, PRST is released and the output of the preamp undergoes a transition determined by VDR. We allow the output node to settle and after about another 50 ns the DRST switch is released. This causes the THSET pulse to cause a small transition at the preamp output, the size of which is determined by VTH.
Both of these transitions do not have any effect on the outputs of the source followers (SF1 and SF2) in the charge driver circuit because they are held during this period at known values controlled by an external voltage (VCLP). The only difference in the output results from any difference in the gains of the source followers. Meanwhile, the capacitor C6 and other stray capacitors (to ground) are charged by the SVX reset current.
The voltage on C6 is equal to the difference between the SVX input bias and VREF. Now the READ switch is opened and the S/H switch is closed. The capacitor C6 now registers the voltage difference between SF1 and SF2. At this point, the PCLP switch is opened and the circuit is ready for acquisition. During the ACQUISITION mode, the preamp is reset after every bunch crossing. In order to minimize any injection at the source followers, PCLP is also exercised during the preamp reset as shown in Figure xx. Any charge at the SIFT input causes a transition which is fed into .
d charge signals into an SVX-II based readout system. The chip R&D is now complete. In this note we present all the measurements that are relevant to the operations of the SIFT. The SIFT chip was initially designed as a trigger "pick-off" chip for the fiber tracker. Hence, the design parameters reflect the requirements of response to minimum ionizing particles (MIP`s) traversing scintillating fibers. The preshower detectors, however, have vastly different signal properties. We have developed a charge division technique in order to increase the effective dynamic range and resolution of the SIFT and adapt it for reading out the preshower detectors.
These studies will be reported in another note. The SIFT chip consists of 20 identical channels, of which 18 will be active and 2 are intended to be guard channels. Figure 1 shows a functional overview of one channel of the SIFT chip. The front-end is an inverting charged sensitive preamplifier with a switched capacitor Cfb (185 fF) in the feedback loop.
The output of the preamp is fed into a buffer source follower that drives ac-coupled discriminator and charge driver circuits. The function of the charge driver circuit is somewhat complicated because it has to regenerate a charge impulse and feed it to the SVX in a dc-coupled mode.
Hence, the dc bias level of the input of the SVX chip has to be offset by the SIFT. The problem becomes more challenging because there is a 20-30 mV variation from channel to channel in this bias level. In order to minimize spurious charge injection due to this variation, the output capacitance of the SIFT has to be small (100 fF) and well controlled.
The circuits used in the preamp and the buffer amplifier are shown in Figure 2. In order to reduce noise in the front-end, a very wide input transistor (with high transconductance) is used. The speed of the integrating circuit is enhanced by the use of a tree of biasing transistors, which step down the stray capacitance.
However, during reset the standing current in the preamp is disturbed and by itself the circuit takes a long time to restore this current to its operating value. In order to speed up this recovery after the feedback capacitor has been reset, an internal pulse, PHDR, is generated across the capacitor C2 (125 fF) capacitor.
The charge induced by this pulse at the preamp output node restores the voltage to its operating point. . An external voltage (VDR) controls the height of this pulse. This procedure allows us to minimize the duration of the reset pulse PRST; we have successfully operated the chip with a reset pulse width of only 5 ns but recommend a 10 ns pulse for normal operation.
Figure 1. : A simplified schematic diagram of one channel of the SIFT chip. The blocks consisting of the preamplifier, the discriminator and the charge transfer circuit are shown. The three controlling voltages, V_DR, VCLMP and VREF are highlighted. discriminator circuit is shown in Figure 3. It operates by setting the bias of the input node at a voltage determined by another internally generated pulse, THSET, which gets divided between the capacitors C9 and C8.
An external voltage (VTH) controls the height of this pulse. The difference between the turn-on voltage of the input transistor and the voltage set at the input node determines the effective threshold voltage of the discriminator. When the output of the preamp is large enough to overcome this difference the discriminator input node switches "on" signaling the presence of a ``hit".
When the S/H pulse is applied, this transition is driven off-chip via a series of inverters. Figure 2: The transistor level circuit diagram of the preamplifier. The voltage V_DR is asserted via an internally generated pulse (not shown) following preamp reset. The discriminator circuit is shown in Figure 3. It operates by setting the bias of the input node at a voltage determined by another internally generated pulse, THSET, which gets divided between the capacitors C9 and C8. An external voltage (VTH) controls the height of this pulse. The difference between the turn-on voltage of the input transistor and the voltage set at the input node determines the effective threshold voltage of the discriminator.
When the output of the preamp is large enough to overcome this difference the discriminator input node switches "on" signaling the presence of a ``hit". When the S/H pulse is applied, this transition is driven off-chip via a series of inverters. Figure 4 shows the charge driver circuit. It consists of two well-matched source followers that have two capacitors, C6 and C7, across their outputs.
The capacitor C7 can be removed from the circuit by turning off the GAIN_SEL switch; in the following discussion we will assume that this is the case. In order to understand the functionality of this circuit, we need to examine the overall operation of the SIFT chip, which consists of a RESET cycle (about 1 us) followed by up to 56 ACQUISITION cycles (132 ns each), depending on the number of bunches in the Tevatron ring.
The RESET cycle is initiated about 300 ns after the SVX reset and it starts with the PRST, DRST, READ and PCLP switches closed. After 10 ns, PRST is released and the output of the preamp undergoes a transition determined by VDR. We allow the output node to settle and after about another 50 ns the DRST switch is released. This causes the THSET pulse to cause a small transition at the preamp output, the size of which is determined by VTH.
Both of these transitions do not have any effect on the outputs of the source followers (SF1 and SF2) in the charge driver circuit because they are held during this period at known values controlled by an external voltage (VCLP). The only difference in the output results from any difference in the gains of the source followers. Meanwhile, the capacitor C6 and other stray capacitors (to ground) are charged by the SVX reset current.
The voltage on C6 is equal to the difference between the SVX input bias and VREF. Now the READ switch is opened and the S/H switch is closed. The capacitor C6 now registers the voltage difference between SF1 and SF2. At this point, the PCLP switch is opened and the circuit is ready for acquisition. During the ACQUISITION mode, the preamp is reset after every bunch crossing. In order to minimize any injection at the source followers, PCLP is also exercised during the preamp reset as shown in Figure xx. Any charge at the SIFT input causes a transition which is fed into .