21062
Technical Summary: ADSP-21062 Digital Signal Processor
Overview
The ADSP-21062 is a high-performance 32-bit digital signal processor (DSP) belonging to the ADSP-21000 family, featuring the SHARC® super Harvard architecture. Designed for demanding signal processing applications, it delivers 40 MIPS performance with a 25 ns instruction rate and single-cycle instruction execution. Its sustained floating-point performance reaches 80 MFLOPS (120 MFLOPS peak), making it ideal for real-time processing in multimedia, communications, and industrial systems.
The processor integrates dual data address generators with modulo and bit-reverse addressing, enabling efficient FFT and other algorithmic operations. Its zero-overhead looping capability ensures optimal execution of repetitive tasks without pipeline stalls. The ADSP-21062 supports multiprocessing through shared memory and link ports, allowing scalable system designs.
Key Features
- Performance: 40 MIPS, 25 ns instruction rate, single-cycle execution
- Floating-Point Capability: 120 MFLOPS peak, 80 MFLOPS sustained
- Memory Architecture: 4M-bit on-chip RAM (split into two 2M-bit blocks)
- Data Addressing: Dual data address generators with modulo and bit-reverse modes
- Program Sequencing: Zero-overhead looping with single-cycle setup
- Multiprocessing Support: Six 4-bit link ports for interprocessor communication
- I/O Interfaces: Two serial ports, host processor interface, and JTAG emulation
- Development Tools: Comprehensive EZ-ICE® emulation support
Applications
The ADSP-21062 is suited for high-performance signal processing applications, including:
- Audio and speech processing (e.g., Dolby Digital, MP3 encoding/decoding)
- Radar and sonar signal processing
- Medical imaging and instrumentation
- Wireless baseband processing (3G/4G, software-defined radio)
- Industrial control and automation
- Multiprocessing systems for compute-intensive tasks
Electrical Characteristics
Recommended Operating Conditions
- Supply Voltage (VDD): 3.3V or 5V (depending on variant)
- Operating Temperature: Commercial (0°C to +70°C) or Industrial (-40°C to +85°C)
- Clock Frequency: Up to 40 MHz (25 ns cycle time)
Timing Specifications
- Memory Read (Bus Master): 25 ns access time
- Memory Write (Bus Master): 25 ns cycle time
- Synchronous Read/Write: Supports synchronous bus protocols
- Link Port Speed: 1× or 2× clock speed operation (up to 80 Mbps per port)
Power Dissipation
- Active Power: 1.5W typical at 40 MHz (5V operation)
- Standby Mode: Reduced power consumption via idle states
Package Information
The ADSP-21062 is available in two package options:
- 225-Ball Plastic Ball Grid Array (PBGA): Compact footprint for space-constrained designs
- 240-Lead Metric PQFP: Traditional quad flat pack for prototyping and testing
PBGA Package Details
- Dimensions: 27mm × 27mm body size, 1.27mm ball pitch
- Ball Configuration: 15 × 15 array (225 balls total)
- Thermal Resistance: 28°C/W (junction-to-ambient)
PQFP Package Details
- Dimensions: 32mm × 32mm body, 0.65mm lead pitch
- Lead Count: 240 leads
- Thermal Resistance: 35°C/W (junction-to-ambient)
Development Tools
Analog Devices provides a robust ecosystem for ADSP-21062 development:
- EZ-ICE Emulator: Real-time debugging with non-intrusive trace
- VisualDSP++ IDE: Integrated development environment with compiler and simulator
- JTAG Support: IEEE 1149.1 compliant test access port for boundary scan
- Evaluation Boards: Reference designs for rapid prototyping
Conclusion
The ADSP-21062 combines high computational throughput with flexible I/O and multiprocessing capabilities, making it a versatile choice for advanced DSP applications. Its balanced architecture—featuring both strong floating-point performance and efficient integer processing—ensures suitability for a wide range of real-time signal processing tasks. With comprehensive development tools and multiple packaging options, designers can leverage this processor across commercial and industrial environments.
