Digital-frequency-window


Posted on Jun 17, 2012

This circuit detects frequency variation above or below preset limits. IC1 is a binary counter docked at FcLK· The outputs are comparea with switch preset values by IC2 and IC3. The input signal, which must be a positive-going pulse, is used to reset IC1. The P greater than Q output of the comparators is at logic 0 for input frequencies below the preset values. Above the preset count, a pulse train is output.


Digital-frequency-window
Click here to download the full size of the above Circuit.

IC2, detects a low input by supplying the pulse train to a retriggerable monostable, IC4. When the input frequency falls below the preset value in SWl, the monostable is no longer triggered and its output falls to logic 0. IC3 detects the frequency high state SW2, and outputs directly when this occurs. The outputs from both comparators can then be latched as shown, using IC5 and IC6. The clock frequency is related to input and switch values: switch value ~ FcLK!i,put· The time constant of IC4 is not critical, but must obviously exceed the maximum input pulse period.




Leave Comment

characters left:

New Circuits

.

 


Popular Circuits

CW Transmitter
Brakelight Stop flasher
Light Dark Sensor With Relay Circuit Using LM741
power window 3 prong safety relay
Wireless Doorbell
Digital dice circuit
Most Accurate Clock
Make your own instrumented glove
Constant Current LED Drive
A typical circuit for the LM4910 two-channel amplifier



Top