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4043

#HCC4043B #HCC4044B #CMOS #quad R/S latch #3-state #NOR #NAND #logic IC #memory storage #signal latching
4043 - HCC4043B/HCC4044B CMOS Quad R/S Latch Technical Summary

4043 - HCC4043B/HCC4044B CMOS Quad R/S Latch Technical Summary

Overview

The HCC4043B and HCC4044B are quad cross-coupled 3-state NOR/NAND R/S latches from the "B" series of high-speed CMOS devices. These integrated circuits provide four independent set/reset latch functions in a single package, making them ideal for applications requiring simple memory storage or signal latching. Manufactured using advanced silicon-gate CMOS technology, these devices offer the low power consumption typical of CMOS while providing improved speed over standard 4000-series parts.

The primary difference between the HCC4043B and HCC4044B lies in their logic implementation: the HCC4043B features NOR-based latches while the HCC4044B uses NAND-based latches. Both versions feature three-state outputs that can be switched to a high-impedance state, allowing for bus-oriented applications.

Key Features

Applications

The HCC4043B/HCC4044B latches find use in numerous digital applications including:

Electrical Characteristics

Absolute Maximum Ratings

DC Characteristics (VDD = 10V, TA = 25°C unless specified)

AC Characteristics (VDD = 10V, TA = 25°C unless specified)

Functional Description

Each of the four latches in the HCC4043B/HCC4044B operates as a basic set/reset flip-flop with three-state output control. The HCC4043B (NOR version) features active-high set and reset inputs, while the HCC4044B (NAND version) uses active-low inputs. Both versions include an active-low enable input that controls all four output buffers simultaneously.

When the enable input is active (low for HCC4043B, high for HCC4044B), the outputs reflect the current state of their respective latches. When disabled, the outputs enter a high-impedance state, allowing multiple devices to share a common bus without contention.

Package Information

Available Packages

Package Dimensions (16-pin DIP)

Pin Configuration

Recommended Operating Conditions

Reliability Information

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